A data latching device, data latch or D latch as referred to herein is a "flip-flop" type device generally used following data generating circuitry to permit temporary storage of currently available data until it is needed. For example in microprocessor based systems where a peripheral to be controlled by the microprocessor is not ready, the microprocessor output data is latched until the peripheral is ready to receive the data while the microprocessor goes on to other calculations. Such data latching devices have at least two modes or states of operation, a transmitting or transparent mode or state for transmitting data signals from the latch input to the output, and a latching mode or state for latching and temporary storage of data previously received at the input. Latch enable gating signals appropriately applied to gates within the latch effect operation and switching between the two modes.
A typical application of such data latches is illustrated in FIG. 2 where is shown an "octal transparent latch" 10 consisting of eight data latches 12, eight tristate output devices or buffers 14, a latch enable signal source LE with inverting delay 15, and output enable signal source OE with inverting delay 16. Such a package of eight latches with eight output buffers is particularly suited for commonly used applications with eight bits to a byte. When a high level voltage appears at the latch enable LE, the latches 12 are in the transparent or transmitting state and data input signals for example in the form of high or low level voltages representing binary 1 and 0 at the inputs D.sub.0 through D.sub.7 are passed through and appear at the outputs O.sub.0 through O.sub.7. Each latch inverts the signal into it as does each buffer 14 so that the outputs at O.sub.0 -O.sub.7 are in phase with the inputs at D.sub.0 -D.sub.7. When the latch enable LE is at low level voltage data previously entered is latched or temporarily stored unchanged in the latches 12 until LE returns to a high level binary "1".
In this application the output buffers 14 perform a number of functions. First, the latch output is a high impedance node and the output buffer 14 transforms impedance to a low impedance node compatible with TTL (transistor-transistor logic) circuits in which the latch can function as an internal device. Additionally, the output buffer devices 14 illustrated in FIG. 2 are tristate output devices with a high impedance third state for applications in which many outputs are tied to a common bus, not shown. When a low level signal OE appears at the output buffers 14 after inversion by inverting delay 16 of a high level signal OE from the output enable, the output gates function as bistate devices delivering high and low level voltages to drive the common bus. When OE is high, tristate output buffers 14 are in the high impedance third state exhibiting a high impedance at the common bus to external circuitry. Further background on such TTL tristate output devices is found in copending U.S. patent applications Ser. No. 005,929, Ser. No. 005,928, and Ser. No. 058,674, all assigned to the assignee of the present invention, namely Fairchild Camera & Instrument Corporation, Mountain View, Calif.